1. Field of the Invention
The present invention relates to a solid-state imaging device. In particular, the present invention relates to a read circuit realizing various read modes such as a block mode (partial read from a specified portion) and a skip mode including interlacing.
2. Description of the Related Art
Conventionally, MOS-type or amplifier-type solid-state imaging devices have been known, in which a signal charge generated from each pixel is read by a read circuit or a signal charge generated by each pixel is converted and amplified to a voltage or current signal in the pixel, and read by the read circuit. In these solid-state imaging devices, by appropriately constructing a read circuit, various read modes such as a block mode (partial read from a specified portion) and a skip mode including interlacing can be performed.
In order to realize various read modes, a decoder is generally used. More specifically, assuming that the total number of drive lines required in a read circuit is m, a B-bit decoder circuit (2.sup.B.gtoreq.m) is used to independently control each drive line, thereby realizing an arbitrary read operation.
However, the drive operation using a decoder has the following problems.
First, according to the drive operation using a decoder, a decoder itself and a B-bit output logic circuit which drives the decoder are required, and the logic circuit is required to generate control signals which are different in accordance with various drive operation modes. Therefore, a large chip area is occupied, increasing power consumption.
Furthermore, according to the drive using a decoder, a circuit does not become equivalent when seen from each drive line. Thus, streak-shaped fixed pattern noise likely occurs.
In order to solve the above-mentioned problems, a scanning circuit for a solid-state imaging device having a special structure as shown in FIGS. 8 and 9 has been proposed (Hosokai et al., "A 4M-Pixel CMD Image Sensor", Technical Report of the Society of Imaging Information Media IPU' 97-15, Mar. 14, 1997). FIG. 9 shows a specific structure of a clocked inverter which is schematically shown in FIG. 8. More specifically, FIG. 9 shows a structure in which CMOS switches are inserted in series in a CMOS inverter circuit.
Among CMOS shift register portions shown in FIG. 8, a portion (I) is driven with a first control signal CK1, a portion (II) is driven with a second control signal CK2, a portion (III) is driven with a third control signal CK3, and a portion (IV) is driven with a fourth control signal CK4.
In the case where only a CMOS shift register portion is composed of the portions (I) and (II), i.e., in the case where lines are successively scanned, a shift pulse is applied to all of the drive lines.
In the case where only a CMOS shift register portion is composed of the portions (I) and (III), i.e., in the case where a 1/2 skip mode is conducted, a shift pulse is successively applied to every other drive line. By controlling a line to which an input signal is input, odd-number lines or even-number lines can be selected, and interlacing can be realized.
In the case where only a CMOS shift register portion is composed of the portions (I) and (IV), i.e., in the case where a 1/4 skip mode is conducted, a shift pulse is successively applied to one line per four drive lines. By controlling a line to which an input signal is input, any of the first, second, third, and fourth lines can be selected from four drive lines.
The scanning circuit for a solid-state imaging device shown in FIG. 8 is provided with a portion (V) for partial reading from a specified portion. Memories M are connected to the shift register via control switches which are opened or closed with a signal CS. The memories M are used for memorizing an electric potential.
Hereinafter, an operation of reading a signal from a specified portion in the CMOS shift register portion will be described. A signal to be read is, for example, a signal related to image information.
First, a write operation for setting a read starting position is performed in a memory M. More specifically, all of the control switches are turned off with the signal CS. Under this condition, the first control signal CK1 and the second control signal CK2 are applied to the shift register portion, and a start pulse is transferred in the clocked inverter. When the start pulse reaches a read position of interest, an electric potential at a low level is recorded in a memory M corresponding to the read position of interest by turning on all of the control switches with the signal CS.
Next, an operation of reading a signal from a specified portion in the CMOS shift register portion is performed. More specifically, all of the control signals are turned on with the signal CS under the condition of the application of the first control signal CK1 and the second control signal CK2. Thus, information of an electric potential is transferred in the shift register from the memory M corresponding to the read position of interest, and a shift pulse is successively output from the read position.
However, the method illustrated in FIG. 8 has the following problems.
First, when partial read is performed from a specified portion in the scanning circuit for a solid-state imaging device in FIG. 8, an operation including two steps: a write operation and a read operation is required. Therefore, in the case of changing a read position successively, an operation is performed only on a 2-frame (write frame and read frame) basis. In other words, a read position cannot be changed successively on a one frame basis.
Furthermore, a skip rate for a skip mode is fixed depending upon a circuit, and hence, cannot be arbitrarily selected. Therefore, it is required to provide circuit portions corresponding to the respective skip rates, such as the portion (III) for a 1/2 skip mode and the portion (IV) for a 1/4 skip mode. As the skip rate is set more variously, the circuit scale is increased.
Furthermore, in the scanning circuit for a solid-state imaging device shown in FIG. 8, a different circuit element such as a memory is required to be added to a simple CMOS shift register, which complicates a circuit.